Bandwidth Introduction: To Be Usable or Not

A common customer question that stems from the most high speed (HS)/RF converter datasheets is: “why is the ADC’s small-signal bandwidth (BW) so broad, as compared to where the datasheet shows the converter’s AC performance and list of analog input frequencies under test?” Many ADC manufacturers tout a much larger BW, more popularly known in conventional converter folklore as full power BW (FPBW). This term, which is typical in most high speed/RF converter datasheets, refers to the amount of BW the ADC needs to accurately “settle” to the ADC’s given datasheet resolution before it moves on to the next sample. When the analog input signal crosses that boundary, the converter starts to degrade rapidly in some cases, by 3 dB or more in many of its AC performance characteristics. Most notably, spurious-free dynamic range (SFDR). In this short paper, we aim to define these differences between the ADC’s “usable” bandwidth (UBW), also sometimes referred to as “sample” bandwidth, and FPBW. UBW describes the frequency range where the ADC’s AC performance remains most useful and predictable. This is also the region where the ADC has typically been characterized, as discussed in the following sections. At the outer edge of FPBW, SFDR can decline rapidly, which makes UBW a more practical indicator of reliable operating bandwidth. UBW provides insight into where that performance boundary starts. Otherwise, trying to use the outer edge of the FPBW can prove disastrous, as performance results will vary. Understanding this difference between the two will more clearly guide the user/designer on how to implement their next analog input frequency plan sufficiently and achieve the expected converter’s dynamic AC performance.

Bandwidth Background

If you pick up a HS/RF converter datasheet, most converters will have good AC performance specified out past fs/2 (baseband or 1st Nyquist). Where “fs” equals the ADC’s sampling rate. Most commonly, you have two Nyquist zones, meaning 1st and 2nd Nyquist, to frequency plan within, or possibly a little more until performance starts to derate at the higher input frequencies. This defines the converter’s usable BW. More information and guidance on Nyquist zones and sampling holes is available in other literature.¹ Although the datasheet may not state this explicitly, the listed test frequencies usually indicate where the ADC was characterized and provide a useful view of its AC dynamic performance robustness, including SFDR. This is found in the ADC’s datasheet specification tables. See Table 1 for an example. In some cases, if you look further down in the datasheet in the “typical performance plots section,” there may be additional frequencies/data that show this performance erosion past the listed frequencies in the specification tables. For an in-depth understanding of AC performance metrics on HS/RF converters such as SFDR and others, please see related information.²

As you can see in the SFDR datasheet snippet of the ADC12DJ3200,⁷ a 12-bit, 3.2 GSPS converter, the test frequency listing starts in the lower MHz region and tests up to near 8.2 GHz, and it has a small-signal FPBW of 7.9 GHz (not shown in Table 1). This is a little “atypical” in nature but gives good insight into how the ADC will perform up to its FPBW and UBW. In this case, it would be prudent to understand the variability in performance past 6.4 GHz. Your AC dynamic performance “mileage” may vary.

Looking at another case, such as the ADC3683-SP,⁸ its datasheet specification tables (see Table 2) show that dynamic AC performance is tested between 1.1 MHz and 70 MHz. However, the analog inputs have a FPBW of 200 MHz (not shown in Table 2), per the datasheet.

If we further explore the AC dynamic performance and begin to measure input frequency tests beyond 70 MHz, as shown in Figure 1, you can see that performance derates quickly. And for input frequencies greater than 90 MHz, the SFDR will rapidly hit 70 dBFS.

More details and tips on measuring HS/RF converter small-signal FPBW are available in the literature.^3,4

FPBW Bandwidth Calculations

As discussed in the previous section, all ADCs will have a settling-time accuracy that is associated with the device’s intended resolution. This means that the HS/RF converter’s internal front-end has enough bandwidth to accurately sample the signal to an LSB of error. Another way to state this is that an ADC’s internal front-end must settle within half a period of the sample clock cycle (0.5/fs, where fs = ADC’s sampling frequency) to provide an in-bounds accurate representation of the analog signal to be acquired at the given sample. Let’s look at an example using the ADC12DJ3200, which is a 12-bit ADC that samples at 3.2 GSPS and has an input voltage full-scale (VFS) range of 0.8 Vpp. The FPBW required can be derived using the following equation using this simple single-pole closed-loop system approach:

V(t) = Vo(1- e^{(-t /}τ)), where τ = 0.35 / BW and τ = Tau = time constants (see Appendix B for derivation); we can use this transient equation by starting with the following:

1 LSB = VFS / (2^N), where LSB = least significant bit, VFS = input voltage full-scale range of the ADC and N = number of ADC bits.

Next, substitute e^{(-t /}τ) for 2^N or 1 LSB = VFS * e^{(-t /}τ), then solve for t.

Note that e^{(-t /}τ) and 2^N are the same fundamental type curve — a natural exponential growth curve.

Where, t = - τ* ln(1 LSB / VFS); next, sub in τ = 0.35 / BW and solve for BW (or FPBW):

t = -(0.35 / FPBW) * ln(1 LSB / VFS); next, sub in t = 1 / fs and solve for FPBW:

FPBW = -(0.35 / (1 / fs) * ln(1 LSB / VFS)) = -(0.35 / (1 / 3.2G) * ln(195.3 u / 800 m)) = 9.315 GHz, derived.

Where: fs = the ADC’s sampling rate.

From the datasheet, we can see the FPBW is 7.9 GHz. Which is in the “ballpark” of the FPBW just derived but obviously not perfect. Keep in mind we are only using a first-order model and have not accounted for parasitics of any kind, e.g., package, PCB and IC.

This FPBW value will yield the minimum required bandwidth of the ADC’s internal front-end FPBW. Therefore, the converter’s internal front-end needs this amount of bandwidth to settle within 1 LSB and sample the analog input signal appropriately.

To understand this a bit more, the ADC will require several time constants to meet this 1 LSB accuracy, where one time constant is equal to -17.1 psec in this case, or:

τ = 0.35 / BW or τ = 1 / (2 * π * FPBW) = 1 / (2 * π * (9.315G)) = 17.086 psec

This corresponds to a rise time, or t_r = 2.2 * τ = 2.2 * 17.086 π = 37.6 psec

We can check this by recalculating the FPBW = 0.35 / t_r = 0.35 / 37.6 p = 9.311 GHz, which is pretty close to the previously derived number: 9.315 GHz.

Usable Bandwidth Calculations

Next, let’s define the usable sample BW or UBW verus the previously found FPBW; the number of time constants needs to be understood for what is required for the full-scale range of the ADC in LSB size, %Full-scale error or VFSE. Therefore, we will find the LSB size in voltage of the ADC first;

or 1 LSB = VFS / (2^N) = 800 m / (2¹²) = 195.3 uVpp.

The %Full-scale error required is equal to (LSB / VFS) * 100 = (195.3 u / 800 m) * 100 = 0.0244 percent.

We can further expand this across different resolution/bit cases to understand the %Full-scale error and derive the number of time constants required for an N-bit ADC to settle within 1 LSB. See Table 3 and Figure 2.

By plotting the exponential function, or e^-t, a graph can be developed that makes it easy to show the relative error with the passing of each time constant. See Figure 2. In the figure, it is shown that it takes 8.3 time constants for the 12-bit ADC example to settle appropriately within 1 LSB. This analysis allows designers to estimate the maximum analog input frequency supported, or UBW that the converter can handle and still settle within 1 LSB of error. Beyond that, the ADC starts to represent the signal inaccurately, and AC dynamic performance will start to degrade, derate or vary; please refer back to Table 1 in this case.

Next, using Table 3 and Figure 2, the number of time constants required by the ADC12DJ3200 is found, and the UBW is represented by the following:

UBW = 1 / (t * number of time constants), 8.3 time constants = 12 bits from Figure 2.

Therefore, the usable sample BW (UBW) = 1 / (17.086 psec * 8.3) = 7.05 GHz, which accurately represents where the AC performance (SFDR) of the converter typically starts to deviate from nominal analog input frequency performance. See Figure 3.

Keep in mind that the assumption here is a single-pole model of the ADC’s internal front-end. Not all HS/RF converters behave this way, but this is a good starting point to get a decent understanding of the ADC’s UBW. These subtle effects can make settling-time calculations stretch beyond first-order, predictable models, especially for higher-resolution converters.

Bandwidth Summary

This short article hopes to give a clear understanding of the difference between a HS/RF converter’s FPBW and UBW. FPBW is the bandwidth needed for the converter to settle accurately to within 1 LSB during a half sampling cycle. Usable sample BW, by contrast, is the analog input frequency range over which the converter can operate while maintaining the expected AC dynamic performance, such as SFDR. Therefore, it is paramount to understand your application frequency planning and BW needs upfront so that when deciding on an ADC for your next design, it will achieve the performance as outlined in your system requirements.

Finally, it’s important to note that this paper tries to outline the perspective of BW around HS/RF converters, and this first-order treatment may not be directly applicable to precision-type converters commonly used in low sampling rate applications (think ksps). These types of converters are architected completely differently and are used in applications where BW is not necessarily a key requirement; it’s more about dynamic range.

Appendix A: ADC3683-SP Calculation Example, 18-Bit, 3.2Vpp Full-Scale, 65MSPS

Using numbers from Table 4, the usable bandwidth of this ADC can be calculated.

t = -(0.35 / FPBW) * ln(1 LSB / VFS); next, sub in t = 1 / fs and solve for FPBW:

FPBW = -(0.35 / (1 / fs) * ln(1 LSB / VFS)) = -(0.35 / (1 / 65M) * ln(12.207 u / 3.2)) = 283.84 MHz, derived

τ = 0.35 / BW or τ = 1 / (2 * p * FPBW) = 1 / (2 * p * (283.84M)) = 560.72 psec

This corresponds to a rise time, or t_r = 2.2 * τ = 2.2 * 560.72 p =1.2336 nsec

We can check this by recalculating the FPBW = 0.35 / t_r = 0.35 / 1.2336n = 283.725 MHz, which is pretty close to the previously derived number: 283.84 MHz.

%Full-scale error, or VFSE. Using 1 LSB = 12.207 uVpp (found above);

The VFSE required is equal to (LSB / VFS) * 100 = (12.207u / 3.2) * 100 = 0.0003815 percent.

UBW = 1 / (τ * number of time constants), 12.5 time constants = 18 bits from Figure 2.

Therefore, the UBW = 1 / (560.72 psec * 12.5) = 142.763 MHz.

Appendix B: Derivation of BW = 0.35 / TR Formula

A simple single-pole system can be modeled as an RC circuit network. From this assumption, we can derive the relationship between BW and rise time (t_r).⁵

Rise time is the time measured from V_out,90% - V_out,10%.

The response for an RC network is V_out = V_in (1 – e^-t / ^τ), where τ = RC.

Since t₁ and t₂ are such that:

t₁and t₂:

t₁ = -τ * ln(1-0.1)=-τ * ln (0.9) = -τ*ln 

= τ * ln = τ * (ln 10-ln9 ) = τ * 0.1054

t₂ = τ * ln 10 = τ * 2.3026

t_r = t₂ - t₁=(2.3 - 0.1) * τ ≅ 2.2 * τ

From the above equation, we can find that t_90% = 2.3 * τ and t_10% = 0.105 * τ.

Therefore, the rise time (or fall time) from, t_10%-90% = 2.3 * τ - 0.105 * τ ≅ 2.2 * τ.

Since BW is defined as the frequency at which the signal is attenuated by 3 dB.

Then, for the simple RC circuit network model, BW = 1 / (2 * π * RC) = 1 / (2 * π * τ).

If we combine the equations for t_10%-90% and BW, we have:

BW = 2.2 / (2 * π * (t_10%-90%)), therefore BW = 0.35 / (t_10%-90%) =0.35 / t_r.

Acknowledgements

The author would like to thank both Brad Brannon and Walt Kester, retired from Analog Devices, but still great mentors and friends, for their guidance and suggestions on this paper.

The author would like to thank Texas Instruments for the use of the datasheet figure snippets. No alterations or changes were made to the individual figures used in this article.

Rob Reeder, Principle Engineer
Analog Signalworks & Next Semiconductor
Analogsignalworks.com, NextSemi.com

References

1. R. Reeder, C. Wood and L. Allen, “Sampling around Nyquist holes in high-speed converters,” Texas Instruments, Web: https://www.ti.com/lit/an/slyt866/slyt866.pdf?ts=1774297753411&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FADC3669.
2. W. Kester, The Data Conversion Handbook, Chapter 5, Newnes, 2005, ISBN 0-7506-7841-0. Also published as Analog-Digital Conversion, Analog Devices, Inc., 2004, ISBN 0-916550-27-3, Web: https://www.analog.com/en/resources/technical-books/data-conversion-handbook.html.
3. R. Reeder and C. Garcia Trujillo, “Proper High-Speed A/D Converter Passband Flatness Revealed: Part 1,” Texas Instruments, Web: https://www.ti.com/lit/an/sdaa191a/sdaa191a.pdf?ts=1774267521923.
4. R. Reeder and C. Garcia Trujillo, “Proper High-Speed D/A Converter Passband Flatness Revealed, Part 2,” Texas Instruments, Web: https://www.ti.com/lit/an/sdaa202/sdaa202.pdf?ts=1774293780410.
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6. E. L. Zuch, “Data Acquisition and Conversion Handbook: A Technical Guide to A/D-D/A Converters and Their Applications,” Datel/Intersil, 1979.
7. ADC12DJ3200 Datasheet, Web: https://www.ti.com/product/ADC12DJ3200.
8. ADC3683-SP Datasheet, Web: https://www.ti.com/lit/ds/symlink/adc3683-sp.pdf?ts=1775966874167.