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Version 6.0.0-Alpha10
Дата публикации: 21-08-2026 00:00:00

We are happy to announce Capstone 6.0.0-Alpha10.
API changes and additions

Enum names of the Alpha architecture are now correctly all upper case.
Because of an old Auto-Sync bug all the enum names were prefixed with Alpha instead of ALPHA
and some contained lower case letters.
Sadly, I just recently recognized that Alpha was effected by that bug.
While this change is very annoying for everybody using the Alpha module,
it must be done before the Beta release.
Please excuse the inconvenience!
A simple command to replace almost all of these occurrences in your code base is:
find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} +

Author: @Rot127


RISC-V got a v5 compatibility macro for its header.
With its recent module update CS_MODE_RISCVC was renamed to CS_MODE_RISCV_C to be
more consistent with the other CS_MODE_ enums.
This could break builds against a v5 code base which only has CS_MODE_RISCVC.
Now you can simply define CAPSTONE_RISCV_COMPAT_HEADER before including capstone.h
and CS_MODE_RISCVC will be defined as alias for CS_MODE_RISCV_C
#define CAPSTONE_RISCV_COMPAT_HEADER
#include <capstone/capstone.h>

Author: @moste00


Prevent literal displacement truncation for AArch64 memory operands.
There are AArch64 displacements which are 64bit in size. But aarch64_op_mem.disp was an int32_t.
It was promoted to an int64_t.
Author: @amaanmujawar


Fixed several decoding bugs in the Alpha module.
See https://github.com/capstone-engine/capstone/pull/2967 for details.
Author: @mattst88


The RISC-V details now also include the FP rounding mode cs_riscv.rounding_mode.
Author: @moste00


AArch64: Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM flag to print shifted MOVN and
MOVZ instructions in their explicit forms instead of using the equivalent MOV aliases.
Example output from cstool:
> cstool aarch64 0xe402a012
mov w4, #-0x170001
> cstool aarch64+explicitwideimm 0xe402a012
movn w4, #0x17, lsl #16
> cstool aarch64+explicitwideimm 0xe402a052
movz w4, #0x17, lsl #16

Author: @amaanmujawar


M68K: Fixed EA decoding error and added ColdFire EMAC_B dual-acc MAC.
Author: @b1llow

See the full release notes at https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha10


Основное содержимое страницы с новостью.

August 21, 2026

We are happy to announce Capstone 6.0.0-Alpha10.

API changes and additions

  • Enum names of the Alpha architecture are now correctly all upper case. Because of an old Auto-Sync bug all the enum names were prefixed with Alpha instead of ALPHA and some contained lower case letters. Sadly, I just recently recognized that Alpha was effected by that bug.

    While this change is very annoying for everybody using the Alpha module, it must be done before the Beta release. Please excuse the inconvenience!

    A simple command to replace almost all of these occurrences in your code base is:

    find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} +

    Author: @Rot127

  • RISC-V got a v5 compatibility macro for its header. With its recent module update CS_MODE_RISCVC was renamed to CS_MODE_RISCV_C to be more consistent with the other CS_MODE_ enums. This could break builds against a v5 code base which only has CS_MODE_RISCVC.

    Now you can simply define CAPSTONE_RISCV_COMPAT_HEADER before including capstone.h and CS_MODE_RISCVC will be defined as alias for CS_MODE_RISCV_C

    #define CAPSTONE_RISCV_COMPAT_HEADER
#include <capstone/capstone.h>

    Author: @moste00

  • Prevent literal displacement truncation for AArch64 memory operands. There are AArch64 displacements which are 64bit in size. But aarch64_op_mem.disp was an int32_t. It was promoted to an int64_t. Author: @amaanmujawar

  • Fixed several decoding bugs in the Alpha module. See https://github.com/capstone-engine/capstone/pull/2967 for details. Author: @mattst88

  • The RISC-V details now also include the FP rounding mode cs_riscv.rounding_mode. Author: @moste00

  • AArch64: Add CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM flag to print shifted MOVN and MOVZ instructions in their explicit forms instead of using the equivalent MOV aliases.

    Example output from cstool:

    > cstool aarch64 0xe402a012
mov w4, #-0x170001

> cstool aarch64+explicitwideimm 0xe402a012
movn w4, #0x17, lsl #16

> cstool aarch64+explicitwideimm 0xe402a052
movz w4, #0x17, lsl #16

    Author: @amaanmujawar

  • M68K: Fixed EA decoding error and added ColdFire EMAC_B dual-acc MAC. Author: @b1llow

See the full release notes at https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha10

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