The post Support RAJA and Scientific Applications on RVV Architectures appeared first on RISC-V International.
![]()
Project Snapshot
In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is a C++ library primarily developed at Lawrence Livermore National Laboratory that offers loop-based abstractions and multiple execution backends to deliver portable performance across heterogeneous systems. We contribute a new RVV backend to RAJA’s vectorization API, enabling RVV-aware optimizations within RAJA-based applications.
In Their Own Words
Poster Preview
Meet the Authors
Hung-Ming is a PhD student in the Department of Computer Science, National Tsing-Hua University, Taiwan. His thesis advisor is Prof. Jenq-Kuen Lee. His research interests are in compiler optimizations on RISC-V with SIMD computations, AI compiler optimizations, and compiler analysis for program reliability.
Dr. Pei-Hung Lin is a computer scientist in the Center for Applied Scientific Computing (CASC) at Lawrence Livermore National Laboratory (LLNL). His research expertise spans compiler optimizations, parallel programming models, and the integration of machine learning techniques into high-performance computing (HPC) workflows. He received his Ph.D. in Computer Science from the University of Minnesota.
Shou-Chen is a graduate student in the Department of Computer Science at National Tsing Hua University, advised by Prof. Jenq-Kuen Lee. His research interests are in compiler optimization on RVV and AI compiler optimization.
Master’s Student in Computer Science at National Tsing Hua University in Taiwan
Chih-Hsi is a master’s student in the Department of Computer Science, National Tsing-Hua University, Taiwan. His advisor is Prof. Jenq-Kuen Lee. His research focuses on register optimizations for RVV and compiler optimizations on RISC-V.
Jenq‑Kuen Lee is a Professor of Computer Science at National Tsing Hua University, Taiwan, specializing in optimizing compilers. He co‑authored Auto‑tuning Fixed‑point Precision with TVM on RISC‑V Packed SIMD (ACM TODAES 2023) and TVM Hybrid‑OP Optimization on RISC‑V SIMD (IEEE Access 2024). His team enhanced SIMDe to automate ARM NEON‑to‑RVV. He presented the RISC‑V ISA for sub‑FP8 at RISC‑V Summit 2024 and maintained contributions across the RISC‑V GitHub ecosystems and TVM upstream on RVV.
| # | Наименование новости | Тональность | Информативность | Дата публикации |
|---|---|---|---|---|
| 1 | We Created a Single Source for All RISC-V Specifications | 0 | 12.73 | 07-05-2026 |
| 2 | Using a Performance Model to Implement a Superscalar CVA6 | 0 | 13.29 | 24-03-2026 |
| 3 | Behind The Scenes of SHD Group’s 2026 RISC-V Market Forecast | 0 | 22.72 | 19-06-2026 |
| 4 | Docker on RISC-V: From Release to Production in 6 Days | 0 | 17.85 | 28-04-2026 |
| 5 | Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SW | 0 | 13.33 | 29-07-2026 |
| 6 | RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual | 0 | 10.88 | 10-02-2026 |
| 7 | Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026 | 0 | 20.36 | 03-03-2026 |
| 8 | Call for Candidates: Help Us Build a Board That Represents Our Entire Ecosystem | 0 | 7.74 | 08-05-2026 |
| 9 | RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart Glasses | 0 | 18.73 | 07-07-2026 |
| 10 | «Рег.облако» внедряет архитектуру Nvidia Blackwell в публичном облаке | 5 | 7 | 23-06-2026 |