The Taiwan Semiconductor Manufacturing Company (TSMC), in partnership with the National Yang Ming Chiao Tung University (NYCU) in Taipei, Taiwan, has made a key breakthrough for next-generation transistor design. TSMC and the NYCU have demonstrated that instead of focusing on depositing new materials on the transistor channel, a better approach is to engineer the channel material to create a buffer before adding the insulating material and then the gate to control the electron flow across the transistor.

Most of today's chips rely on either FinFET (fin field-effect) or GaaFET (gate-all-around) transistors to transfer and manage current. These transistors are three-dimensional structures. They rely on a channel that protrudes upwards around which the gate is wrapped. This approach allows for a greater contact area between the gate and the channel to allow for improved control of the current flow. In a transistor, the channel is responsible for the current flow, while the gate is responsible for controlling the flow.

However, advances in chip manufacturing technology, which allow manufacturers such as TSMC to reduce channel thickness to 5 nanometers and make the channels shorter to squeeze more transistors into a chip, make it difficult for transistor gates to control electron flow.

As the channel length approaches 3 nanometers to 5 nanometers, it makes the gate ineffective in controlling the electron flow. Similarly, for channel thicknesses below roughly 3 nanometers, electrons moving through the channel come into contact with the gate, which increases resistance.

Samsung Foundry's diagram showing the evolution of a transistor from FinFET to GAAFET and then MBCFET. The 3nm process from the Korean company will utilize GAAFET transistors, which it has developed in partnership with International Business Machines Corporation (IBM). Image: Samsung Electronics The breakthrough illustrated in a diagram. Image: Nature Electronics (2026). DOI: 10.1038/s41928-026-01672-7

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In order to solve these constraints, chip manufacturers have been researching two-dimensional monolayer transistors. Since these transistors are one molecular layer thick, they enable greater gate control and lower resistance while allowing chip manufacturers to increase transistor density across a chip by aiming at 0.7 nanometer channel thickness and less than 3 nanometer channel length.

However, the thinness of the material introduces its own set of challenges. Research into these transistors revealed that manufacturing the gate through traditional deposition techniques led to an uneven gate dielectric layer over the channel due to the characteristics of the monolayer molybdenum disulfide (MoS₂) transistor channel material. MoS₂ is used due to its natural 0.7-nanometer thickness and its ability to support greater current control. On the other hand, FinFET transistors mostly use Silicon-Germanium as the channel material.

TSMC and NYCU's research aimed to overcome the limitations of depositing the gate material on the channel. Specifically, their research focused on the gate dielectric layer that prevents leakage and enables current control. As opposed to previous techniques, which investigated novel deposition approaches or new materials, the pair instead relies on an ultrathin epitaxial aluminum layer.

They engineered the MoS₂ surface by depositing the aluminum layer and allowed it to oxidize to form a 0.42-nanometer-thick aluminum oxide. After the layer was formed, the high-κ hafnium oxide gate dielectric material was added on top of it.

Through the surface engineering, the researchers demonstrated that the new approach allows for tighter flow control and reduced resistance in an MoS₂ transistor at a level similar to the dielectric layer being 1-nanometer thick.

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